Stuck at Fault Model Archives

Applying S@ Faults with a Simulator: An Introduction

When I introduced you to the Stuck at Fault Model I stated that the size of VLSI devices necessitated the usage of Electronic Design Automation (EDA) tools to support testing.

My first full-time job at IBM exposed me to the world of test and to their EDA tools.

In the mid-1980’s, testing of logic devices relied upon the S@ fault model. Three common software tools included fault simulation, automatic test pattern generation, and fault diagnosis.

This article will provide an introduction to fault simulation as one can view the other two tools as applications built upon a fault simulator. [Read more…]

by Anne Meixner Leave a Comment

Stuck at Testing of Digital Combinational Logic—Part 2

In the previous article you learned to apply the Stuck at Fault Model (S@) to a small combinational circuit.

You can take the learning on the Full 1-bit adder and apply it to larger combinational circuit.

In testing lingo, you often hear people refer to this as the testing of random logic. Technically, there’s nothing random about the logic.

I think “random” gets used to contrast with the highly structured design of memory circuits into array of 1-bit cells. Memory test lends itself to algorithmic testing, for example the Marching 1. In random logic testing you may use algorithms to propagate your faults, that is automatically develop a test pattern.

You need to keep in mind that the logic being tested has a functional purpose and this can be implemented in a multitude of ways. Let’s take a second look at the adder function. [Read more…]

by Anne Meixner Leave a Comment

Stuck at Testing of Digital Combinational Logic—Part 1

To work our ways towards understanding Design For Test (DFT)applications I am taking you back to the Stuck at Fault model (S@).

In the article which introduced you to the S@ model you learned the S@ model at the logic gate level.

Let’s build on this by applying it to combinational logic circuits.

Combinational logic has no clocked circuitry; sequential logic has clocked circuitry. In a few articles you’ll learn about test and sequential logic circuitry. [Read more…]

by Anne Meixner 1 Comment

What Makes Memory Test Hard

Just One More Thing

Memory circuits store 1’s and 0’s for you so that you can retrieve them later. The 1/0’s can represent data or instructions.

Today, no computing device operates without some memory. Memory devices store pictures, music, documents. How many USB (Unified Serial Bus) memory sticks do you have scattered on your desk?

Semiconductor memory comes in many flavors: Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Read Only Memory (ROM), Erasable Programmable Memory (EPROM), NAND/NOR Memory (a.k.a. Flash), Solid State Drive (SSD). Without power volatile memories like SRAM and DRAM lose their stored values. Non-Volatile memories retain their stored value when power is absence. [Read more…]

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Digital Circuits and the Stuck at Fault Model

Semiconductor Integrated Circuits (ICs) can have millions of digital circuits which can translate to billions of transistors.

I know these numbers can be intimidating, but I assure you the challenges of testing ICs started in the mid-late 1970’s. Lots of effort has been put into Electronic Design Automation (EDA) systems and Design for Test (DFT) techniques to manage the development and application of digital circuit testing.

In the beginning these software programs and DFT techniques used the Stuck at Fault Model. [Read more…]