Degradation

Testing performed to measure any degradation in the reliability of a product over the course of production or to assure that products being delivered meet customer’s reliability requirements and/or expectations.

A mathematical relationship describing the a) the rate of a degradation mechanism or the time-to-failure, and b) the conditions or stresses that caused the degradation.

Equipment that is designed to automatically conduct analysis of functional or static parameters and to evaluate the degree of UUT (Unit Under Test) performance degradation; and may be used to perform fault isolation of UUT malfunctions. The decision making, control, or evaluative functions are conducted with minimum reliance on human intervention and usually done under computer control.

A failure mechanism in silicon based electronic devices. It describes the phenomenon by which carriers gain sufficient energy to be injected into the gate oxide. This occurs as carriers move along the channel in MOSFET and experience impact ionization near the drain end of the device. The damage can occur at the interface, within the oxide and/or within the sidewall spacer. Interface-state generation and charge trapping induced by this mechanism result in transistor parameter degradation, typically switching frequency degradation, rather than a “hard’ functional failure. (Reference JEP122F)