Accendo Reliability

Your Reliability Engineering Professional Development Site

  • Home
  • About
    • Contributors
  • Reliability.fm
    • Speaking Of Reliability
    • Rooted in Reliability: The Plant Performance Podcast
    • Quality during Design
    • Critical Talks
    • Dare to Know
    • Maintenance Disrupted
    • Metal Conversations
    • The Leadership Connection
    • Practical Reliability Podcast
    • Reliability Matters
    • Reliability it Matters
    • Maintenance Mavericks Podcast
    • Women in Maintenance
    • Accendo Reliability Webinar Series
    • Asset Reliability @ Work
  • Articles
    • CRE Preparation Notes
    • on Leadership & Career
      • Advanced Engineering Culture
      • Engineering Leadership
      • Managing in the 2000s
      • Product Development and Process Improvement
    • on Maintenance Reliability
      • Aasan Asset Management
      • CMMS and Reliability
      • Conscious Asset
      • EAM & CMMS
      • Everyday RCM
      • History of Maintenance Management
      • Life Cycle Asset Management
      • Maintenance and Reliability
      • Maintenance Management
      • Plant Maintenance
      • Process Plant Reliability Engineering
      • ReliabilityXperience
      • RCM Blitz®
      • Rob’s Reliability Project
      • The Intelligent Transformer Blog
    • on Product Reliability
      • Accelerated Reliability
      • Achieving the Benefits of Reliability
      • Apex Ridge
      • Metals Engineering and Product Reliability
      • Musings on Reliability and Maintenance Topics
      • Product Validation
      • Reliability Engineering Insights
      • Reliability in Emerging Technology
    • on Risk & Safety
      • CERM® Risk Insights
      • Equipment Risk and Reliability in Downhole Applications
      • Operational Risk Process Safety
    • on Systems Thinking
      • Communicating with FINESSE
      • The RCA
    • on Tools & Techniques
      • Big Data & Analytics
      • Experimental Design for NPD
      • Innovative Thinking in Reliability and Durability
      • Inside and Beyond HALT
      • Inside FMEA
      • Integral Concepts
      • Learning from Failures
      • Progress in Field Reliability?
      • Reliability Engineering Using Python
      • Reliability Reflections
      • Testing 1 2 3
      • The Manufacturing Academy
  • eBooks
  • Resources
    • Accendo Authors
    • FMEA Resources
    • Feed Forward Publications
    • Openings
    • Books
    • Webinars
    • Journals
    • Higher Education
    • Podcasts
  • Courses
    • 14 Ways to Acquire Reliability Engineering Knowledge
    • Reliability Analysis Methods online course
    • Measurement System Assessment
    • SPC-Process Capability Course
    • Design of Experiments
    • Foundations of RCM online course
    • Quality during Design Journey
    • Reliability Engineering Statistics
    • Quality Engineering Statistics
    • An Introduction to Reliability Engineering
    • An Introduction to Quality Engineering
    • Process Capability Analysis course
    • Root Cause Analysis and the 8D Corrective Action Process course
    • Return on Investment online course
    • CRE Preparation Online Course
    • Quondam Courses
  • Webinars
    • Upcoming Live Events
  • Calendar
    • Call for Papers Listing
    • Upcoming Webinars
    • Webinar Calendar
  • Login
    • Member Home

by Anne Meixner 1 Comment

The Test Attributes of Controllability and Observability

If a tree falls in a forest with no one around to hear it, does it still make a sound?

If a fault occurs in a combinational circuit but its masked at the outputs is it still a fault?

If you can’t excite a fault from the circuit inputs does it really exist?

If you can’t propagate a fault to an output pin, does it matter?

In assessing an integrated circuit’s testability engineers consider the concepts of controllability and observability. In these specific characteristics of testability came up often the academic test literature of the 1970’s and 1980’s. The challenge back then was automatic test generation and fault simulation.

Concepts

I’ll use the definitions provided by Abramovici, Breuer and Friedman in their book “Digital Systems Testing and Testable Design.” From Chapter 9, Design for Testability:

Controllability: ability to establish a specific signal value at each node in a circuit from setting values at the circuit’s inputs.

Observability: ability to determine the signal value at any node in a circuit by controlling the circuit’s inputs and observing its outputs.

A circuit’s design impacts a circuit’s controllability and observability. These attributes impact an algorithm’s for generating tests (a subject for future articles). Test generation costs less for circuits with better controllability and observability. Design For Test (DFT) techniques improve these attributes which lead to increased fault coverage, decreased test generation costs and often decreased test time.

Often techniques address both controllability and observability. Though let’s start alphabetically with controllability.

Controllability Techniques

Recall in How to Test Clocked Circuits that you needed an ability to set the initial state. That’s a controllability need.

One way to do it is at power-on initialize the latch/flip-flop to an initial state. That’s partial solution.  You can only choose one state.  For complete controllability you need to be able to set the value to 0 and a 1. You can then have two ways of setting the latches:  A clear- set all to a 0 and a pre-set to an initial value.  Designers may add such features, as they too want some predictability in how the circuit will behave. However, a designer when presetting a values has a mission/functional mode in mind.  For test purposes you need more control.

An ad-hoc technique to increase controllability is adding a test point- adding a signal that you can control externally.

For larger circuits you can divide and conquer. Consider a counter, these can be difficult to test because of all the clock cycles to go through all the states. A 16-bit counter takes 65536 cycles, split that into two 8-bit counters and you get 256 cycles per partition. Test them in parallel and you have halved the test time.

Scan Based design increases both controllability and observability. You are able to set internal states and observe internal states. Full Scan design means all latches/flip-flops are part of the scan chain. Partial scan design means you are selective in the latches/flip-flops that become part of the scan chain.

Observability Techniques

Any technique which enhances your ability to observe a particular state counts. Turns out most of the controllability techniques double as an observability technique.

Adding a test point which connects an internal state to an external pin provides additional observability. This can become expensive in terms of output pins.  You can trade-off area and time by using a scan register to capture internal node values and connect this to an external pin. You can do the same for controlling a node values with a scan-register controlled by a test point.

DFT Tradeoffs When Increasing Controllability and Observability

Like all engineering tasks generating tests to cover all IC faults involves trade-offs. You may have noticed that improving controllability and observability techniques costs additional hardware (pins, interconnect or circuits). The benefit is typically shorter computation of tests generated, higher test quality for less test patterns. There are also collateral benefits- increased observability makes it easier for you to do fault isolation and then you need to do.

You can mitigate some of the costs. Which hardware cost have you seen as the most to be used?

Meanwhile remember testing takes time and thoughtful application,

Anne Meixner, PhD

Additional Reading:

If you like philosophical discussions of the “If the tree falls….” I found this to be a light personal thread on the Guardian. If you want to go deeper check out the Wikipedia articleWikipedia article.

Abramovici, Breuer and Friedman’s book “Digital Systems Testing and Testable Design” available on Amazon.

Abramovici et al also describe another term which I have not often heard used in my professional circles but I believe upon reading makes sense to raise to your awareness as it captures all the other subtle things that can impact the ability to test a circuit:

Predictability: ability to obtain knowns output values in response to given input stimuli.

Factors that affect predictability should be red flags to anyone dealing with electronics repeatability and reliability: Initial state of a circuit, races, hazards and free-running oscillators.

Filed Under: Articles, on Tools & Techniques, Testing 1 2 3 Tagged With: Design For Test, Digital Test, Mastery 2

« Ten Second Tease – 3 Methods for Crafting the Ultimate Elevator Speech
Critical Success Factors for Risk Based Thinking »

Comments

  1. V.MANUEL JEYANESAN says

    October 11, 2021 at 1:28 PM

    what are the contributes of the observability and controllability sir i need answer for my question immediately

    Reply

Leave a Reply Cancel reply

Your email address will not be published. Required fields are marked *

Article by Anne Meixner
in the Testing 1 2 3 series

Join Accendo

Receive information and updates about articles and many other resources offered by Accendo Reliability by becoming a member.

It’s free and only takes a minute.

Join Today

Recent Posts

  • What is the Difference Between Quality Assurance and Quality Control?
  • Covariance of the Kaplan-Meier Estimators?
  • Use Of RFID In Process Safety: Track Hazardous Chemicals And Track Personnel
  • How to Reduce Maintenance Cost The Right Way
  • Significance Over Success. Innovation Over Change. Anticipation Over Agility

© 2023 FMS Reliability · Privacy Policy · Terms of Service · Cookies Policy

This site uses cookies to give you a better experience, analyze site traffic, and gain insight to products or offers that may interest you. By continuing, you consent to the use of cookies. Learn how we use cookies, how they work, and how to set your browser preferences by reading our Cookies Policy.