Articles tagged Digital Test

The Test Attributes of Controllability and Observability

If a tree falls in a forest with no one around to hear it, does it still make a sound?

If a fault occurs in a combinational circuit but its masked at the outputs is it still a fault?

If you can’t excite a fault from the circuit inputs does it really exist?

If you can’t propagate a fault to an output pin, does it matter?

In assessing an integrated circuit’s testability engineers consider the concepts of controllability and observability. In these specific characteristics of testability came up often the academic test literature of the 1970’s and 1980’s. The challenge back then was automatic test generation and fault simulation. [Read more…]

by Anne Meixner Leave a Comment

Labor Saving DFT: Built-In Self-Test

In honor of Labor Day, I thought I would jump over to the Built-In Self-Test (BIST) wing of the DFT Castle.

I will provide you with a quick tour. Then when you hear the term in a meeting you can follow along and ask a few questions.

BIST saves labor for the Automatic Test Equipment (ATE).

Though there’s no free lunch. BIST does require an engineer to labor—someone has to design it specific to the device under test (DUT). [Read more…]

by Anne Meixner Leave a Comment

A Primer on Design For Test

In a previous article I alluded to Design for Test (DFT) by mentioning a specific example.

The techniques have been around for decades. Just how long ago though?

I searched on “Design for Test” in the IEEE paper data base; the search resulted in 760 references the oldest being 1983.

Hmm there had to be earlier papers? So next I plugged in the key words “Design For Testability.” This time a list of 4,235 references appeared, the oldest one published in 1978. [Read more…]

by Anne Meixner Leave a Comment

Applying S@ Faults with a Simulator: An Introduction

When I introduced you to the Stuck at Fault Model I stated that the size of VLSI devices necessitated the usage of Electronic Design Automation (EDA) tools to support testing.

My first full-time job at IBM exposed me to the world of test and to their EDA tools.

In the mid-1980’s, testing of logic devices relied upon the S@ fault model. Three common software tools included fault simulation, automatic test pattern generation, and fault diagnosis.

This article will provide an introduction to fault simulation as one can view the other two tools as applications built upon a fault simulator. [Read more…]

by Anne Meixner Leave a Comment

Stuck at Testing of Digital Combinational Logic—Part 2

In the previous article you learned to apply the Stuck at Fault Model (S@) to a small combinational circuit.

You can take the learning on the Full 1-bit adder and apply it to larger combinational circuit.

In testing lingo, you often hear people refer to this as the testing of random logic. Technically, there’s nothing random about the logic.

I think “random” gets used to contrast with the highly structured design of memory circuits into array of 1-bit cells. Memory test lends itself to algorithmic testing, for example the Marching 1. In random logic testing you may use algorithms to propagate your faults, that is automatically develop a test pattern.

You need to keep in mind that the logic being tested has a functional purpose and this can be implemented in a multitude of ways. Let’s take a second look at the adder function. [Read more…]

by Anne Meixner Leave a Comment

Stuck at Testing of Digital Combinational Logic—Part 1

To work our ways towards understanding Design For Test (DFT)applications I am taking you back to the Stuck at Fault model (S@).

In the article which introduced you to the S@ model you learned the S@ model at the logic gate level.

Let’s build on this by applying it to combinational logic circuits.

Combinational logic has no clocked circuitry; sequential logic has clocked circuitry. In a few articles you’ll learn about test and sequential logic circuitry. [Read more…]

by Anne Meixner Leave a Comment

Digital Circuits and the Stuck at Fault Model

Semiconductor Integrated Circuits (ICs) can have millions of digital circuits which can translate to billions of transistors.

I know these numbers can be intimidating, but I assure you the challenges of testing ICs started in the mid-late 1970’s. Lots of effort has been put into Electronic Design Automation (EDA) systems and Design for Test (DFT) techniques to manage the development and application of digital circuit testing.

In the beginning these software programs and DFT techniques used the Stuck at Fault Model. [Read more…]