
To work our ways towards understanding Design For Test (DFT)applications I am taking you back to the Stuck at Fault model (S@).
In the article which introduced you to the S@ model you learned the S@ model at the logic gate level.
Let’s build on this by applying it to combinational logic circuits.
Combinational logic has no clocked circuitry; sequential logic has clocked circuitry. In a few articles you’ll learn about test and sequential logic circuitry. [Read more…]














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